<html><body><samp><pre>
<!@TC:1606337969>
#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug  4 2017
#install: D:\yhpsoft\Diamond\diamond\3.10_x64\synpbase
#OS: Windows 7 6.1
#Hostname: FPGA-USE

# Thu Nov 26 04:59:29 2020

#Implementation: impl1

<a name=compilerReport4></a>Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017</a>
@N: : <!@TM:1606337970> | Running in 64-bit mode 
Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

<a name=compilerReport5></a>Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017</a>
@N: : <!@TM:1606337970> | Running in 64-bit mode 
Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

@N: : <!@TM:1606337970> | : Running Verilog Compiler in System Verilog mode 
@N: : <!@TM:1606337970> | : Running Verilog Compiler in Multiple File Compilation Unit mode 
@I::"D:\yhpsoft\Diamond\diamond\3.10_x64\synpbase\lib\lucent\machxo2.v" (library work)
@I::"D:\yhpsoft\Diamond\diamond\3.10_x64\synpbase\lib\lucent\pmi_def.v" (library work)
@I::"D:\yhpsoft\Diamond\diamond\3.10_x64\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"D:\yhpsoft\Diamond\diamond\3.10_x64\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
@I::"D:\yhpsoft\Diamond\diamond\3.10_x64\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"D:\yhpsoft\Diamond\diamond\3.10_x64\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"F:\home\mini-mcu\hardware\mcu\step_fpga\clk_gen.v" (library work)
@I::"F:\home\mini-mcu\hardware\mcu\step_fpga\top.v" (library work)
@I::"F:\home\mini-mcu\hardware\mcu\step_fpga\divide.v" (library work)
@I::"F:\home\mini-mcu\hardware\mcu\step_fpga\mcu.v" (library work)
@I::"F:\home\mini-mcu\hardware\mcu\step_fpga\rom.v" (library work)
Verilog syntax check successful!
Selecting top level module LED_shining
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="F:\home\mini-mcu\hardware\mcu\step_fpga\divide.v:13:7:13:13:@N:CG364:@XP_MSG">divide.v(13)</a><!@TM:1606337970> | Synthesizing module divide in library work.

	N=32'b00000000000011110100001001000000
   Generated name = divide_1000000s
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="F:\home\mini-mcu\hardware\mcu\step_fpga\divide.v:63:1:63:7:@W:CL169:@XP_MSG">divide.v(63)</a><!@TM:1606337970> | Pruning unused register clk_n. Make sure that there are no unused intermediate registers.</font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="F:\home\mini-mcu\hardware\mcu\step_fpga\divide.v:53:1:53:7:@W:CL169:@XP_MSG">divide.v(53)</a><!@TM:1606337970> | Pruning unused register cnt_n[19:0]. Make sure that there are no unused intermediate registers.</font>
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="F:\home\mini-mcu\hardware\mcu\step_fpga\mcu.v:3:7:3:10:@N:CG364:@XP_MSG">mcu.v(3)</a><!@TM:1606337970> | Synthesizing module mcu in library work.
<a name=error6></a><font color=red>@E:<a href="@E:CS153:@XP_HELP">CS153</a> : <a href="F:\home\mini-mcu\hardware\mcu\step_fpga\mcu.v:91:15:91:16:@E:CS153:@XP_MSG">mcu.v(91)</a><!@TM:1606337970> | Can't mix blocking and non-blocking assignments to a variable</font>
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Nov 26 04:59:30 2020

###########################################################]
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Nov 26 04:59:30 2020

###########################################################]

</pre></samp></body></html>
